PCI stands for "peripheral component interface" defined by the PCI Special Interest Group in an effort to stem development of various local bus architectures. The PCI bus may be connected to adapters requiring fast inter-adapter access and/or system memories with accesses near to the host processor native bus speed. Read and write transfers over the PCI bus are burst transfers with any negotiated length defined by the initiating and target device. The prior art is familiar with PCI bus architectures.
The prior art is also familiar with PCI bridge chips that connect together two PCI buses. These bridge chips can be used, for example, in transferring data from an initiating PCI bus to a target PCI bus. One prior art bridge chip is the DEC21154 chip from Intel, for example. Such prior art bridge chips generally provide for sequential transfer of large bursts of data across the bridge; though they cannot effectively handle multiple delayed requests and completions without regard to the order in which they were received or completed.
Some prior art PCI bridges do not provide for delayed transactions, which are instead handled sequentially. Other prior art PCI bridges implement delayed transactions, but place ordering restrictions on either the requests or the completions. These bridges thus either implement a single delayed transaction, or multiple delayed transactions which require completion in a specific order relative to being received on the initiating bus and completion on the target bus.
The prior art bridge chips present a problem, for example, in SCSI RAID controller systems--known in the art--where the primary data path is not across the bridge. SCSI (Small Computer System Interface) defines a bus interface that is typically used between a host computer and associated data storage devices, such as the RAID (Redundant Array of Inexpensive or Independent Disks). In dual PCI bus SCSI RAID controller systems, the bridge is used to transfer small command blocks between the central processing unit ("CPU") of the host computer and the other devices in the system. A single large burst provided by prior art PCI bridges offers little performance advantage to SCSI RAID controller systems.
SCSI RAID controller systems would thus benefit from a PCI bridge chip which processes multiple command blocks simultaneously; and one object of the invention is thus to provide such a PCI bridge chip.
Another object of the invention is to provide a PCI bridge chip that sacrifices large data bursts in favor of multiple, small bursts, that are typical of command traffic seen in a SCSI RAID system.
Yet another object of the invention is to provide a PCI bridge chip that handles multiple SCSI requests efficiently and in parallel, instead of sequentially as in the prior art. Still another object of the invention is to provide an improved RAID controller with increased bandwidth and I/O's (inputs and outputs) per second.
These and other objects will become apparent in the description that follows.